The present invention relates to a logic level converter circuit and more particularly to a logic level converter circuit for converting high and low logic voltage levels into different high and low logic levels.
A word line driver circuit has been proposed as a level converter circuit which converts high and low logic voltage levels into different high and low logic levels. Such a word line driver circuit is disclosed in ISSCC'95 DIGEST OF TECHNICAL PAPERS "Circuit Design Techniques For Low-Voltage Operating And/Or Giga-Scale DRAMs". FIG. 1 is a circuit diagram illustrative of such the conventional word line driver circuit for converting the high and low logic voltage levels into different high and low logic levels, wherein the HIGH level corresponding to an internal power voltage VINT is converted into a different high voltage level corresponding to a boosting power voltage VPP whilst the LOW level corresponding to the ground level GND is converted into a different low voltage level corresponding to a shallow voltage level VBB.
To reduce a sub-threshold leakage current, a word line voltage is controlled at a negative voltage level in a stand-by state and controlled at a boosting voltage level higher than the internal operation voltage level in an active state.
In the above word line driver circuit, a node A3 is driven by an output from a ROW decoder as a logic gate. It is now considered that the node A3 is indirectly driven by a driver in another block. FIG. 3 is a block diagram illustrative of the other conventional word line driver circuit for converting the high and low logic voltage levels into different high and low logic levels, wherein the node A3 is indirectly driven by a driver in another block. Input waveforms from an inverter D3 of the other block has large rise and fall-times since an input signal from the inverter D3 is transmitted through a load of a line H1 into an input section VIN. For this reason, a transition time of the logic voltage level at the input section VIN is large, whereby a large punch through current I1 flows from the power source VPP through the line H1 and transistors Q2 and Q5 to the ground GND in response to the fall of the voltage level from the inverter D3. In addition, a large punch through current I2 flows from the power source VINT through the line H1 and transistors Q6 and Q4 to the power source VBB in response to the rise of the voltage level from the invertor D3. In order to avoid problems with the large punch through currents, it is preferable that the node A3 is directly driven by the output from the logic gate.
The following description will focus on circuit configurations and operations of the conventional level converter circuit as illustrated in FIG. 2 wherein a node A3 is directly driven by an inverter D2. FIG. 4 is a timing chart illustrative of waveforms of the conventional level converter circuit as illustrated in FIG. 2. The conventional level converter circuit has an input section and a driver section. The driver section of the conventional level converter circuit has p-channel MOS field effect transistors Q1 and Q2 having a substrate voltage VPP as well as has n-channel MOS field effect transistors Q3 and Q4 having a substrate voltage VBB. The input section of the conventional level converter circuit has an n-channel MOS field effect transistor Q5 having a substrate voltage of ground level and a gate which receives a voltage VINT. The input section of the conventional level converter circuit also has a p-channel MOS field effect transistor Q6 having a substrate voltage of VINT and a gate which is applied with a voltage of ground level. The input section of the conventional level converter circuit also has an inverter D2 comprising n-channel and p-channel MOS field effect transistors which have the same size as the n-channel and p-channel MOS field effect transistors Q5 and Q6 respectively.
In the input section, the inverter D2 has an input side connected to an input terminal VIN of the conventional level converter circuit and an output side connected to a node A3. The n-channel MOS field effect transistor Q5 is connected in series between the node A3 and a node A1, whilst the p-channel MOS field effect transistor Q6 is connected in series between the node A3 and a node A2.
First, rising operation of the output voltage VOUT is considered. When the input voltage VIN is in the ground level GND, then the node A3 in the output side of the invertor D2 has the voltage level VINT, whilst the node A2 has the voltage level VINT and the output terminal VOUT has the voltage level VBB. The transistors Q5, Q1 and Q4 are in the non-conductive states or OFF state, whilst the remaining transistors Q6, Q2 and Q3 are in the conductive state or ON state whereby the individual nodes are connected to the power voltages.
When the input voltage VIN rises from the ground level GND to the voltage level VINT, the potential of the node A3 is dropped from the voltage level VINT to the ground level GND. Since at this time the transistor Q6 is in the ON state, then the potential of the node A2 falls to approach an absolute value .vertline.VTP.vertline. of a negative threshold voltage VTP of the p-channel transistor, whereby the source and drain voltage of the transistor Q6 or the voltage applied across the nodes A2 and A3 is reduced. As a result, the driving ability of the transistor Q6 is dropped and the potential of the node A2 is gradually dropped.
On the other hand, since the potential of the node A3 is dropped to a voltage level defined as a difference of VINT-VTN wherein VTN is a positive threshold voltage of the n-channel MOS field effect transistors, the transistor Q5 turns to a conductive state or ON state, whereby the potential of the node A1 falls. When the potential of the node A1 becomes not higher than a voltage level of VPP-.vertline.VTP.vertline., the transistor Q1 turns ON whereby the voltage level of the output VOUT gradually rises because the transistor Q3 has remained in the conductive state or the ON state. Thereafter, when the voltage level of the output terminal VOUT rises to not lower than a voltage level VBB+VTN, then the transistor Q4 turns to the conductive state or the ON state, whereby the potential of the node A2 falls to the voltage level VBB. As a result, the transistors Q3 and Q6 turn to an OFF state or the non-conductive state. At this time, the output voltage VOUT rises to the voltage level VPP and the transistors Q1 and Q5 are in the conductive state or the ON state.
Subsequently, the falling operation of the output voltage VOUT will be considered. When the input voltage VIN is in the voltage level VINT, then the node A3 is in the ground level GND, the node A2 is in the voltage level VBB and the output voltage VOUT is in the voltage level VPP. The transistors Q6, Q2 and Q3 are in the non-conductive state or OFF state whilst the remaining transistors Q5, Q1 and Q4 are in the conductive state or ON state so that the individual nodes are connected to the power voltages.
When the input voltage VIN is dropped from the voltage level VINT to the ground level GND, then the node A3 rises from the ground level GND to the voltage level VINT. Since at this time the transistor Q5 is in the conductive state or ON state, then the node A1 voltage level rises to approach the voltage level defined as VINT-VTN.
Since the source and drain voltage of the transistor Q5 or the voltage applied across the nodes A1 and A3 is reduced, the driving ability of the transistor Q5 drops and the potential of the node A1 gradually rises.
On the other hand, since the potential of the node A3 is risen to a voltage level defined as a difference of .vertline.VTP.vertline., the transistor Q6 turns the conductive state or ON state, whereby the potential of the node A2 rises. When the potential of the node A2 becomes not lower than a voltage level of VBB+VTN, the transistor Q3 turns ON whereby the voltage level of the output VOUT is gradually dropped. Thereafter, when the voltage level of the output terminal VOUT is dropped to not higher than a voltage level VPP-.vertline.VTP.vertline., then the transistor Q2 turns to the conductive state or the ON state, whereby the potential of the node A1 is risen to the voltage level VPP. As a result, the transistors Q1 and Q5 turn OFF state or the non-conductive state. At this time, the output voltage VOUT is dropped to the voltage level VBB and the transistor Q4 is in the non-conductive state or OFF state and the transistors Q3 and Q6 are in the conductive state or the ON state.
In the above manner as described above, the level converter circuit converts the logic levels, for example, HIGH level: VINT corresponding to the internal power voltage and LOW level: GND corresponding to the ground level into different logic levels, for example, HIGH level: VPP corresponding to the booster power voltage and LOW level: VBB negative low voltage VBB.
In the above conventional level converter circuit, the inverter D2 is operated as an input logic gate on the input section, whilst the transistors Q5 and Q6 are operated as transfer gate transistors for preventing the logic level of the node A3 from being transferred to the voltage level VPP or VBB. On the input section of the above conventional level converter circuit, the output from the input logic gate or the voltage level of the node A3 is transferred through the transfer gate transistors Q5 and Q6 to the nodes A1 and A2 so that those outputs from the transfer gate transistors Q5 and Q6 or the voltage levels of the nodes A1 and A2 are inputted into the driver section.
The above conventional level converter circuit has the following problems.
In the rise operation of the output voltage VOUT, the p-channel MOS field effect transistor Q1 on the driver section is driven by the plural transistors, for example, the n-channel MOS field effect transistor of the invertor D2 acting as the input logic gate on the input section and the n-channel transfer gate MOS field effect transistor Q5 on the input section.
Further, in the fall operation of the output voltage VOUT, the n-channel MOS field effect transistor Q3 on the driver section is driven by the plural transistors, for example, the p-channel MOS field effect transistor of the invertor D2 acting as the input logic gate on the input section and the p-channel transfer gate MOS field effect transistor Q6 on the input section.
Since each of the driver transistors on the driver section is driven by the plural transistors on the input section, the above conventional level converter circuit is incapable of exhibiting high speed logic level conversion operations.
In the above circumstances, it had been required to develop a novel level converter circuit free from the above problems.